Future Si CMOS scaling is reaching practical and fundamental limits. The strained-Si technology (SiGe embedded S/D etc.) is gradually approaching its limits as a performance booster in non-planar devices due to the challenges of integration. In order to reduce power while maintaining performance for future technology nodes, high mobility materials, such as Ge and III-V together with advanced device structures are being aggressively explored to increase the drive current and reduce switching times. Current research focuses on: