@article{zhai_fabrication_2012,
title = {Fabrication of {Three}-{Dimensional} {MIS} {Nano}-{Capacitor} {Based} on {Nanoimprinted} {Single} {Crystal} {Silicon} {Nanowire} {Arrays}},
volume = {4},
abstract = {We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications.},
number = {4},
journal = {Micro and Nanosystems},
author = {Zhai, Yujia and Palard, Marylene and Mathew, Leo and Mustafa Hussain, Muhammad and Grant Willson, C. and Tutuc, Emanuel and K. Banerjee, Sanjay},
month = dec,
year = {2012},
keywords = {atomic layer deposition, Bosch Process Cycles, Capacitor, Dram, Eot, FinFETs, lithography, Nano-Imprint, nanowire, Planar Structure, Si Etching, Si-Nanowires, TEM Micrographs, UV Nano-Imprint Lithography, Vapor-Liquid-Solid},
pages = {333--338}
}
@article{zhai_high-performance_2012,
title = {High-{Performance} {Flexible} {Thin}-{Film} {Transistors} {Exfoliated} from {Bulk} {Wafer}},
volume = {12},
issn = {1530-6984},
url = {http://dx.doi.org/10.1021/nl302735f},
doi = {10.1021/nl302735f},
abstract = {Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for the fabrication of inexpensive, high-performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be prefabricated on bulk silicon wafer with the conventional complementary metal?oxide?semiconductor (CMOS) process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to producing thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).},
number = {11},
urldate = {2016-02-15},
journal = {Nano Lett.},
author = {Zhai, Yujia and Mathew, Leo and Rao, Rajesh and Xu, Dewei and Banerjee, Sanjay K.},
month = nov,
year = {2012},
pages = {5609--5615}
}
@article{tao_uniform_2012,
title = {Uniform {Wafer}-{Scale} {Chemical} {Vapor} {Deposition} of {Graphene} on {Evaporated} {Cu} (111) {Film} with {Quality} {Comparable} to {Exfoliated} {Monolayer}},
volume = {116},
issn = {1932-7447},
url = {http://dx.doi.org/10.1021/jp3068848},
doi = {10.1021/jp3068848},
abstract = {This article demonstrated monolayer graphene grown on annealed Cu (111) films on standard oxidized 100-mm Si wafers with higher quality than existing reports. Large area Raman mapping indicated high uniformity ({\textgreater}97\% coverage) of monolayer graphene with immeasurable defects ({\textgreater}95\% defect-negligible) across the entire wafer. Key to these results is the phase transition of evaporated copper films from amorphous to (111) preferred crystalline, which resulted in subsequent growth of high quality graphene, as corroborated by X-ray diffraction and electron backscatter diffraction. Noticeably, such phase transition of the copper film was observed on a technologically ubiquitous Si wafer with a standard amorphous thermal oxide. A modified two-step etching transfer process was introduced to preserve the clean surface and electrical property of transferred monolayer graphene. The fabricated graphene field effect transistor on a flexible polyimide film achieved peak mobility over 4900 cm2/(V s) at ambient condition.},
number = {45},
urldate = {2016-02-15},
journal = {J. Phys. Chem. C},
author = {Tao, Li and Lee, Jongho and Holt, Milo and Chou, Harry and McDonnell, Stephen J. and Ferrer, Domingo A. and Babenco, Matías G. and Wallace, Robert M. and Banerjee, Sanjay K. and Ruoff, Rodney S. and Akinwande, Deji},
month = nov,
year = {2012},
pages = {24068--24074}
}
@inproceedings{sarkar_remote_2012,
title = {Remote plasma chemical vapor deposition for high-efficiency ultra-thin \#x223C;25-microns crystalline {Si} solar cells},
doi = {10.1109/PVSC-Vol2.2012.6656713},
abstract = {For the first time, a remote plasma chemical vapor deposition (RPCVD) based c-Si/a-Si heterojunction solar cell process was developed on thin crystalline silicon semiconductor-on-metal (SOM) substrate. In RPCVD systems, deposition temperature, deposition rate, and the distance of the sample from the plasma source can be varied to minimize the surface damage and enhance passivation quality. A silicon heterojunction (HJ) cell without intrinsic a-Si layer passivation was fabricated on an exfoliated ∼25µm c-Si SOM foil, with an efficiency of 13.4\% and open-circuit voltage of 645mV. Losses in these devices were analyzed by numerical simulations and optimum device structure was designed and performance predicted.},
booktitle = {Photovoltaic {Specialists} {Conference} ({PVSC}), {Volume} 2, 2012 {IEEE} 38th},
author = {Sarkar, D. and Onyegam, E.U. and Saha, S. and Mathew, L. and Rao, R.A. and Hilali, M.M. and Smith, R.S. and Xu, D. and Jawarani, D. and Garcia, R. and Stout, R. and Gurmu, A. and Ainom, M. and Fossum, J.G. and Banerjee, S.K.},
month = jun,
year = {2012},
keywords = {amorphous silicon, Computer architecture, Heterojunctions, Metals, Microprocessors, Passivation, Photovoltaic cells, remote plasma CVD, Silicon, Solar cells, thin silicon},
pages = {1--6}
}
@article{register_bilayer_2012,
title = {Bilayer {Pseudo}-{Spin} {Field} {Effect} {Transistor} ({BiSFET}): {Concepts} and {Critical} {Issues} for {Realization}},
volume = {45},
issn = {1938-6737, 1938-5862},
shorttitle = {Bilayer {Pseudo}-{Spin} {Field} {Effect} {Transistor} ({BiSFET})},
url = {http://ecst.ecsdl.org/content/45/4/3},
doi = {10.1149/1.3700447},
abstract = {The Bilayer pseudo-spin Field Effect Transistor (BiSET) has been proposed as one means of taking advantage of possible room temperature superfluidity in two graphene layers separated by a thin dielectric. In principle, the switching energy per device could be on the scale of 10 zJ, over two orders of magnitude below estimates for "end-of the roadmap" CMOS transistors. However, achieving both the goal of room temperature superfluidity and harnessing it for low-power switching pose substantial challenges, both theoretical and experimental. In this work we review the basic graphene superfluidity and BiSFET concepts, our current understanding―and limits to that understanding―of the requirements for condensate formation, and how these requirements could impact BiSFET design.},
language = {en},
number = {4},
urldate = {2016-02-15},
journal = {ECS Trans.},
author = {Register, Leonard F. and Mou, X. and Reddy, Dharmendar and Jung, Wooyoung and Sodemann, Inti and Pesin, Dima and Hassibi, Arjang and MacDonald, Allan H. and Banerjee, Sanjay K.},
month = apr,
year = {2012},
pages = {3--14}
}
@inproceedings{reddy_bilayer_2012,
title = {Bilayer graphene vertical tunneling field effect transistor},
doi = {10.1109/DRC.2012.6256932},
abstract = {Electronic devices have been explored in the past based on resonant single-electron CB (conduction band) to CB tunneling between parallel quasi-two dimensional (2D) quantum wells within III-V heterostructures and their accompanying negative differential resistance (NDR) [1]. Such devices are attractive for high speed electronics, and digital logic circuits also have been demonstrated using a combination of conventional and such NDR FETs [2]. For two graphene layers separated by a tunnel barrier, we recently proposed the ultra-low-voltage Bilayer pseudoSpin FET (BiSFET) which would employ enhanced nonresonant VB (valence band) to CB tunneling, with a nevertheless very sharp NDR characteristic based on a predicted room-temperature many-body superfluid state [3]. However, NDR due to resonant single-particle CB-to-CB or VB-to-VB tunneling may also be achievable in such a structure. Furthermore, the atomically near-perfect 2D nature of the component graphene layers and the conduction/valence band symmetry may offer advantages over III-Vs. Here, we model the I-V characteristics due to single-particle tunneling in such a structure, Fig. 1, using a perturbative tunneling Hamiltonian approach [4,5], and deviations from this simple theory using atomistic tight-binding nonequilibrium Green's function (NEGF) simulation.},
booktitle = {Device {Research} {Conference} ({DRC}), 2012 70th {Annual}},
author = {Reddy, D. and Register, L.F. and Banerjee, S.K.},
month = jun,
year = {2012},
keywords = {bilayer graphene, BiSFET, C, CB tunneling, component graphene layers, conduction bands, digital logic circuits, Field effect transistors, graphene, Green's function methods, Logic gates, low-power electronics, many-body superfluid state, NDR FET, Negative differential resistance, nonequilibrium Green function, parallel quasi-2D quantum wells, perturbative tunneling Hamiltonian approach, quantum wells, resonant single electron conduction band, resonant tunnelling, single particle tunneling, temperature 293 K to 298 K, tunnel barrier, tunnel transistors, ultra low voltage bilayer pseudospin FET, valence bands, valence band symmetry, vertical tunneling field effect transistor},
pages = {73--74}
}
@inproceedings{ramon_graphene_2012,
title = {Graphene frequency doubler with record 3GHz bandwidth and the maximum conversion gain prospects},
doi = {10.1109/MWSYM.2012.6259401},
abstract = {We report a 500nm graphene field-effect transistor operating at the Dirac point for frequency doubling with maximum output power of −23dBm and a record bandwidth of 3GHz, 2× higher than the state-of-the-art. The experimental device exceeds its ft and fmax by about 50\%. Contact resistance degrades the performance of the experimental GFET. In the limit of negligible non-idealities and maximum gate capacitance, the conversion gain approaches lossless frequency doubling. The record performance of the graphene doubler is enabled by the growth of high-quality graphene affording carrier mobilities as high as 5000cm2/V-s and 2200cm2/V-s on smooth quartz and flexible substrates respectively.},
booktitle = {Microwave {Symposium} {Digest} ({MTT}), 2012 {IEEE} {MTT}-{S} {International}},
author = {Ramon, Michael E. and Parrish, Kristen N. and Lee, Jongho and Magnuson, Carl W. and Tao, Li and Ruoff, Rodney S. and Banerjee, S.K. and Akinwande, Deji},
month = jun,
year = {2012},
keywords = {Conversion gain, doubler, flexible electronics, Frequency conversion, Gain, graphene, Logic gates, mobility, nanoscale, Quantum capacitance, Substrates, Transistors},
pages = {1--3}
}
@article{ramon_three-gigahertz_2012,
title = {Three-{Gigahertz} {Graphene} {Frequency} {Doubler} on {Quartz} {Operating} {Beyond} the {Transit} {Frequency}},
volume = {11},
issn = {1536-125X},
doi = {10.1109/TNANO.2012.2203826},
abstract = {We demonstrate a 500-nm graphene frequency doubler with a record 3-GHz bandwidth, exceeding the device transit frequency by 50\%, a previously unobserved result in graphene, indicating that graphene multiplier devices might be useful beyond their transit frequency. The maximum conversion gain of graphene ambipolar frequency doublers is determined to approach a near lossless value in the quantum capacitance limit. In addition, the experimental performance of graphene transistor frequency detectors is demonstrated, showing responsivity of 25.2 μA/μW. The high-frequency performance of these gigahertz devices is enabled by top-gate device fabrication using synthesized graphene transferred onto low capacitance, atomically smooth quartz substrates, affording carrier mobilities as high as 5000 cm2/V ·s.},
number = {5},
journal = {IEEE Transactions on Nanotechnology},
author = {Ramón, M.E. and Parrish, K.N. and Chowdhury, S.F. and Magnuson, Carl W. and Movva, H.C.P. and Ruoff, R.S. and Banerjee, Sanjay K. and Akinwande, D.},
month = sep,
year = {2012},
keywords = {atomically smooth quartz substrates, Bandwidth, C, doubler, frequency 3 GHz, Frequency conversion, frequency multipliers, Gain, gigahertz devices, graphene, graphene ambipolar frequency doublers, graphene multiplier devices, graphene transistor frequency detectors, high-frequency performance, maximum conversion gain, microwave transistors, Performance evaluation, Quantum capacitance, quantum capacitance limit, quartz, radio frequency devices, size 50 nm, synthesized graphene, three-gigahertz graphene frequency doubler, top-gate device fabrication, Transistors, transit frequency},
pages = {877--883}
}
@article{nah_role_2012,
title = {Role of {Confinement} on {Carrier} {Transport} in {Ge}–{SixGe}1–x {Core}–{Shell} {Nanowires}},
volume = {12},
issn = {1530-6984},
url = {http://dx.doi.org/10.1021/nl2030695},
doi = {10.1021/nl2030695},
abstract = {We examine the impact of shell content and the associated hole confinement on carrier transport in Ge?SixGe1?x core?shell nanowires (NWs). Using NWs with different SixGe1?x shell compositions (x = 0.5 and 0.7), we fabricate NW field-effect transistors (FETs) with highly doped source/drain and examine their characteristics dependence on shell content. The results demonstrate a 2-fold higher mobility at room temperature, and a 3-fold higher mobility at 77K in the NW FETs with higher (x = 0.7) Si shell content by comparison to those with lower (x = 0.5) Si shell content. Moreover, the carrier mobility shows a stronger temperature dependence in Ge?SixGe1?x core?shell NWs with high Si content, indicating a reduced charge impurity scattering. The results establish that carrier confinement plays a key role in realizing high mobility core?shell NW FETs.},
number = {1},
urldate = {2016-02-15},
journal = {Nano Lett.},
author = {Nah, Junghyo and Dillen, David C. and Varahramyan, Kamran M. and Banerjee, Sanjay K. and Tutuc, Emanuel},
month = jan,
year = {2012},
pages = {108--112}
}
@article{movva_self-aligned_2012,
title = {Self-aligned graphene field-effect transistors with polyethyleneimine doped source/drain access regions},
volume = {101},
issn = {0003-6951, 1077-3118},
url = {http://scitation.aip.org/content/aip/journal/apl/101/18/10.1063/1.4765658},
doi = {10.1063/1.4765658},
abstract = {We report a method of fabricating self-aligned, top-gated graphene field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped source/drain access regions, resulting in a 2X reduction of access resistance and a 2.5X improvement in device electrical characteristics, over undoped devices. The GFETs on Si / SiO 2 substrates have high carrier mobilities of up to 6300 cm 2 / Vs . Self-aligned spin-on-doping is applicable to GFETs on arbitrary substrates, as demonstrated by a 3X enhancement in performance for GFETs on insulating quartz substrates, which are better suited for radio frequency applications.},
number = {18},
urldate = {2016-02-15},
journal = {Applied Physics Letters},
author = {Movva, Hema C. P. and Ramón, Michael E. and Corbet, Chris M. and Sonde, Sushant and Chowdhury, Sk Fahad and Carpenter, Gary and Tutuc, Emanuel and Banerjee, Sanjay K.},
month = oct,
year = {2012},
keywords = {Carrier mobility, Doping, Electrical resistivity, Etching, graphene},
pages = {183113}
}
@inproceedings{kim_etb-qw_2012,
title = {{ETB}-{QW} {InAs} {MOSFET} with scaled body for improved electrostatics},
doi = {10.1109/IEDM.2012.6479151},
abstract = {This paper reports Extremely-Thin-Body (ETB) InAs quantum-well (QW) MOSFETs with improved electrostatics down to Lg = 50 nm (S =103 mV/dec, DIBL = 73 mV/V). These excellent metrics are achieved by using extremely thin body (1/3/1 nm InGaAs/InAs/InGaAs) quantum well structure with optimized layer design and a high mobility InAs channel. The ETB channel does not significantly degrade transport properties as evidenced by gm {\textgreater}1.5 mS/μm and vinj = 2.4 × 10 cm/s.},
booktitle = {Electron {Devices} {Meeting} ({IEDM}), 2012 {IEEE} {International}},
author = {Kim, T.-W. and Kim, D. and Koh, D.-H. and Hill, R.J.W. and Lee, R.T.P. and Wong, M.H. and Cunningham, T. and Del Alamo, J.A. and Banerjee, S.K. and Oktyabrsky, S. and Greene, A. and Ohsawa, Y. and Trickett, Y. and Nakamura, G. and Li, Q. and Lau, K.M. and Hobbs, C. and Kirsch, P.D. and Jammy, R.},
month = dec,
year = {2012},
keywords = {Aluminum oxide, Electrostatics, ETB channel, ETB-QW MOSFET, extremely-thin-body quantum-well MOSFET, high mobility channel, III-V semiconductors, Immune system, improved electrostatics, InAs, indium compounds, Logic gates, MOSFET, MOSFET circuits, optimized layer design, scaled body, semiconductor quantum wells, Silicon, thin body quantum well structure, Transconductance},
pages = {32.3.1--32.3.4}
}
@article{jadaun_density_2012,
series = {Exploring {Graphene}, {Recent} {Research} {Advances}},
title = {Density functional theory studies of interactions of graphene with its environment: {Substrate}, gate dielectric and edge effects},
volume = {152},
issn = {0038-1098},
shorttitle = {Density functional theory studies of interactions of graphene with its environment},
url = {http://www.sciencedirect.com/science/article/pii/S0038109812002505},
doi = {10.1016/j.ssc.2012.04.044},
abstract = {This paper reviews the theoretical work undertaken using density functional theory (DFT) to explore graphene's interactions with its surroundings. We look at the impact of substrates, gate dielectrics and edge effects on the properties of graphene. In particular, we focus on graphene-on-quartz and graphene-on-alumina systems, exploring their energy spectrum and charge distribution. Silicon-terminated quartz is found to not perturb the linear graphene spectrum. On the other hand, oxygen-terminated quartz and both terminations of alumina bond with graphene, leading to the opening of a band gap. Significant charge transfer is seen between the graphene layer and the oxide in the latter cases. Additionally, we review the work of others regarding the effect of various substrates on the electronic properties of graphene. Confining graphene to form nanoribbons also results in the opening of a band gap. The value of the gap is dependent on the edge properties as well as width of the nanoribbon.},
number = {15},
urldate = {2016-02-15},
journal = {Solid State Communications},
author = {Jadaun, Priyamvada and Sahu, Bhagawan R. and Register, Leonard F. and Banerjee, Sanjay K.},
month = aug,
year = {2012},
keywords = {A. Graphene, A. Thin films, D. Electronic transport},
pages = {1497--1502}
}
@article{hilali_enhanced_2012,
title = {Enhanced photocurrent in thin-film amorphous silicon solar cells via shape controlled three-dimensional nanostructures},
volume = {23},
issn = {0957-4484},
url = {http://stacks.iop.org/0957-4484/23/i=40/a=405203},
doi = {10.1088/0957-4484/23/40/405203},
abstract = {In this paper, we have explored manufacturable approaches to sub-wavelength controlled three-dimensional (3D) nano-patterns with the goal of significantly enhancing the photocurrent in amorphous silicon solar cells. Here we demonstrate efficiency enhancement of about 50\% over typical flat a-Si thin-film solar cells, and report an enhancement of 20\% in optical absorption over Asahi textured glass by fabricating sub-wavelength nano-patterned a-Si on glass substrates. External quantum efficiency showed superior results for the 3D nano-patterned thin-film solar cells due to enhancement of broadband optical absorption. The results further indicate that this enhanced light trapping is achieved with minimal parasitic absorption losses in the deposited transparent conductive oxide for the nano-patterned substrate thin-film amorphous silicon solar cell configuration. Optical simulations are in good agreement with experimental results, and also show a significant enhancement in optical absorption, quantum efficiency and photocurrent.},
language = {en},
number = {40},
urldate = {2016-02-15},
journal = {Nanotechnology},
author = {Hilali, Mohamed M. and Yang, Shuqiang and Miller, Mike and Xu, Frank and Banerjee, Sanjay and Sreenivasan, S. V.},
year = {2012},
pages = {405203}
}
@patent{colombo_establishing_2012,
title = {Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene},
url = {http://www.google.com/patents/US8198707},
abstract = {A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.},
nationality = {United States},
assignee = {Board Of Regents, The University Of Texas System},
number = {US8198707 B2},
urldate = {2016-02-15},
author = {Colombo, Luigi and Banerjee, Sanjay and Kim, Seyoung and Tutuc, Emanuel},
month = jun,
year = {2012},
note = {U.S. Classification 257/635, 438/591, 257/E21.085, 257/E29.001, 257/415; International Classification H01L29/00, H01L21/18; Cooperative Classification H01L21/28255, H01L29/1606, H01L29/51, H01L29/513; European Classification H01L21/28E3, H01L29/16G}
}
@inproceedings{chang_possible_2012,
title = {Possible applications of topological insulator thin films for tunnel {FETs}},
doi = {10.1109/DRC.2012.6256984},
abstract = {We have begun to explore the possibility of thin film three dimensional (3D) topological insulator (TI) based tunnel FETs (TFETs), specifically Bi2Se3 here, using quantum ballistic transport simulations with a tight-binding Hamiltonian in the atomic orbital basis including spin degrees of freedom. TI-based TFETs would be analogous in some ways to graphene nanoribbon TFETs, but without the sensitivity to ribbon width and edge roughness, and in some ways to narrow gap III-V TFETs but with substantially thinner quantum well widths.},
booktitle = {Device {Research} {Conference} ({DRC}), 2012 70th {Annual}},
author = {Chang, Jiwon and Register, L.F. and Banerjee, S.K.},
month = jun,
year = {2012},
keywords = {3D topological insulator, atomic orbital basis, ballistic transport, Bi2Se3, bismuth compounds, edge roughness, Field effect transistors, graphene, graphene nanoribbon, Logic gates, nanoribbons, quantum ballistic transport simulation, quantum well width, ribbon width, semiconductor quantum wells, spin degrees of freedom, TFET, thin films, TI based tunnel FET, tight-binding Hamiltonian, topological insulator thin film, tunnel transistors},
pages = {31--32}
}
@article{chang_topological_2012,
title = {Topological insulator {Bi}2Se3 thin films as an alternative channel material in metal-oxide-semiconductor field-effect transistors},
volume = {112},
issn = {0021-8979, 1089-7550},
url = {http://scitation.aip.org/content/aip/journal/jap/112/12/10.1063/1.4770324},
doi = {10.1063/1.4770324},
abstract = {Three-dimensional (3-D) topological insulators (TIs) are characterized by the presence of metallic surface states and a bulk band gap. Recently, theoretical and experimental studies have shown an induced gap in the surface state bands of TI thin films. The gap results from interaction of conduction band and valence band surface states from the opposite surfaces of a thin film, and its size is determined by the film thickness. This gap formation could open the possibility of thin-film TI-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Here we explore the performance of MOSFETs based on TI thin films, specifically Bi2Se3, using quantum ballistic transport simulations with the tight-binding Hamiltonian in the atomic orbital basis. Our simulations indicate that Bi2Se3 MOSFET will be vulnerable to short-channel effects due to the high relative dielectric constant of Bi2Se3 (∼100) despite its expected excellent electrostatic integrity inherent in a two-dimensional system, and will have other limitations as compared to silicon–based MOSFETs. However, Bi2Se3 MOSFETs, and presumably other TI-based MOSFETs, appear to provide reasonable performance that perhaps could provide novel device opportunities when combined with novel TI properties such as spin-polarized surface states.},
number = {12},
urldate = {2016-02-15},
journal = {Journal of Applied Physics},
author = {Chang, Jiwon and Register, Leonard F. and Banerjee, Sanjay K.},
month = dec,
year = {2012},
keywords = {Band structure, dielectric constant, Metallic thin films, MOSFETs, Surface states},
pages = {124511}
}
@article{cervantes-gonzalez_germanium_2012,
title = {Germanium metal-semiconductor-metal photodetectors evanescently coupled with upper-level silicon oxynitride dielectric waveguides},
volume = {101},
issn = {0003-6951, 1077-3118},
url = {http://scitation.aip.org/content/aip/journal/apl/101/26/10.1063/1.4773212},
doi = {10.1063/1.4773212},
abstract = {We demonstrate Ge-on-Si metal-semiconductor-metal (MSM) photodetectors monolithically integrated with silicon oxynitride (SiOxNy) waveguides. The waveguide is placed on top of the photodetector and between the metalelectrodes, evading the shading effect by metalelectrodes, which is typical in surface-illuminated MSM photodetectors. The devices showed responsivity of about 0.45 A/W for 80 μm long devices at 1550 nm. The photodetector with 1.5 μm electrode spacing showed 3 dB bandwidth of 2.0 GHz at −2 V and 2 μA dark current. Further studies suggest that with a modified design the structure is capable of achieving 1 A/W responsivity and greater bandwidth.},
number = {26},
urldate = {2016-02-15},
journal = {Applied Physics Letters},
author = {Cervantes-González, Juan C. and Ahn, Donghwan and Zheng, Xiaoguang and Banerjee, Sanjay K. and Jacome, Alfonso T. and Campbell, Joe C. and Zaldivar-Huerta, Ignacio E.},
month = dec,
year = {2012},
keywords = {Electrodes, Elemental semiconductors, Germanium, Optical waveguides, Photodetectors},
pages = {261109}
}
@patent{banerjee_bi-layer_2012,
title = {Bi-layer pseudo-spin field-effect transistor},
url = {http://www.google.com/patents/US8188460},
abstract = {A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.},
nationality = {United States},
assignee = {Board Of Regents, The University Of Texas System},
number = {US8188460 B2},
urldate = {2016-02-15},
author = {Banerjee, Sanjay K. and Leonard, Franklin Register II and MacDonald, Allan and Palle, Dharmendar Reddy and Tutuc, Emanuel},
month = may,
year = {2012},
note = {U.S. Classification 257/39, 257/36, 438/158; International Classification H01L29/06; Cooperative Classification H01L29/7781, B82Y10/00, H01L29/7831, H01L29/1606, H01L29/775; European Classification H01L29/775, H01L29/78E, B82Y10/00, H01L29/16G, H01L29/778B}
}
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