2011.bib

@article{yum_epitaxial_2011,
  title = {Epitaxial {ALD} {BeO}: {Efficient} {Oxygen} {Diffusion} {Barrier} for {EOT} {Scaling} and {Reliability} {Improvement}},
  volume = {58},
  issn = {0018-9383},
  shorttitle = {Epitaxial {ALD} {BeO}},
  doi = {10.1109/TED.2011.2170073},
  abstract = {In a previous study, we demonstrated that the BeO film grown by atomic layer deposition (ALD) on Si and III-V metal-oxide-semiconductor devices has excellent electrical and physical characteristics. In this paper, we discuss the physical and electrical properties of ALD BeO as an oxygen diffusion barrier on scaled 4-nm HfO2/BeO gate stacks. Thin BeO layers are deposited onto (100) p-Si substrates as an alternative to SiO2 as an interfacial passivation layer (IPL). X-ray photoelectron spec troscopy and transmission electron microscopy show that the BeO IPL acts as an effective oxygen barrier against SiOιι. native oxide formation during postdeposition annealing (PDA). The use of ALD BeO as an oxygen diffusion barrier results in lower equivalent oxide thickness, more competitive leakage current, and better reliability characteristics after PDA than Al2O3 and HfO2 gate stacks.},
  number = {12},
  journal = {IEEE Transactions on Electron Devices},
  author = {Yum, Jung Hwan and Bersuker, G. and Akyol, T. and Ferrer, D.A. and Lei, Ming and Park, Keun Woo and Hudnall, T.W. and Downer, M.C. and Bielawski, C.W. and Yu, E.T. and Price, J. and Lee, Jack C. and Banerjee, Sanjay K.},
  month = dec,
  year = {2011},
  keywords = {(100) p-Si substrates, Aluminum oxide, annealing, Atomic-layer-deposited (ALD) beryllium oxide (BeO), atomic layer deposition, BeO, beryllium compounds, beryllium oxide (BeO) interfacial layer passivation (IPL), Dielectrics, diffusion barriers, electrical properties, EOT reliability improvement, EOT scaling improvement, epitaxial ALD, epitaxial growth, epitaxial layers, film growth, gate stacks, hafnium compounds, interfacial passivation layer, leakage current, leakage currents, Logic gates, lower equivalent oxide thickness, native oxide formation, oxygen diffusion barrier, Passivation, physical properties, postdeposition annealing, reliability, Si, Silicon, Substrates, thin layers, transmission electron microscopy, X-ray photoelectron spectra, X-ray photoelectron spectroscopy},
  pages = {4384--4392}
}
@article{sahu_edge_2011,
  title = {Edge saturation effects on the magnetism and band gaps in multilayer graphene ribbons and flakes},
  volume = {84},
  url = {http://link.aps.org/doi/10.1103/PhysRevB.84.075481},
  doi = {10.1103/PhysRevB.84.075481},
  abstract = {Using a density functional theory based electronic structure method and semilocal density approximation, we study the interplay of geometric confinement, magnetism, and external electric fields on the electronic structure and the resulting band gaps of multilayer graphene ribbons, the edges of which are saturated with molecular hydrogen (H2) or hydroxyl (OH) groups. We discuss the similarities and differences of computed features in comparison with the atomic hydrogen (or H-) saturated ribbons and flakes. For H2 edge saturation, we find shifted labeling of three armchair ribbon classes and magnetic to nonmagnetic transition in narrow zigzag ribbons, the critical width of which changes with the number of layers. Other computed characteristics, such as the existence of a critical gap and external electric field behavior, layer-dependent electronic structure, stacking-dependent band-gap induction, and the length confinement effects remain qualitatively the same with those of H-saturated ribbons.},
  number = {7},
  urldate = {2016-02-15},
  journal = {Phys. Rev. B},
  author = {Sahu, Bhagawan and Min, Hongki and Banerjee, Sanjay K.},
  month = aug,
  year = {2011},
  pages = {075481}
}
@article{register_stepped_2011,
  title = {Stepped {Broken}-{Gap} {Heterobarrier} {Tunneling} {Field}-{Effect} {Transistor} for {Ultralow} {Power} and {High} {Speed}},
  volume = {32},
  issn = {0741-3106},
  doi = {10.1109/LED.2011.2126038},
  abstract = {The concept and the simulated device characteristics of ultralow-power and high-performance band-to-band tunneling field-effect transistors employing stepped broken-gap heterobarriers, HetTFETs, are presented. Abrupt switching is defined by the onset of a band overlap. High on-state currents are provided by narrow tunnel barriers defined by crystal growth rather than electrostatics. Sentaurus Device simulations exhibit current roll-offs by approximately 106 over ranges of 15 meV down to a few millielectronvolts, depending on the prototype device structure, and approximately constant above-threshold transconductance values approaching current CMOS-like values.},
  number = {6},
  journal = {IEEE Electron Device Letters},
  author = {Register, L.F. and Hasan, M.M. and Banerjee, Sanjay K.},
  month = jun,
  year = {2011},
  keywords = {band-to-band tunneling field effect transistors, Beyond complementary metal–oxide–semiconductor (beyond-CMOS), broken-gap heterobarrier, CMOS integrated circuits, crystal growth, HetTFET, high electron mobility transistors, high speed application, Logic gates, low-power electronics, Semiconductor device modeling, Sentaurus device simulation, stepped broken gap heterobarrier tunneling transistor, Switches, Transistors, Tunneling, tunneling field-effect transistor (HetTFET), tunnel transistors, ultralow power application},
  pages = {743--745}
}
@article{reddy_graphene_2011,
  title = {Graphene field-effect transistors},
  volume = {44},
  issn = {0022-3727},
  url = {http://stacks.iop.org/0022-3727/44/i=31/a=313001},
  doi = {10.1088/0022-3727/44/31/313001},
  abstract = {Owing in part to scaling challenges for metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) logic, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved MOSFET performance beyond the 22 nm node, or provide novel functionality for, e.g. 'beyond CMOS' devices. Graphene, with its novel and electron–hole symmetric band structure and its high carrier mobilities and thermal velocities, is one such material that has garnered a great deal of interest for both purposes. Single and few layer carbon sheets have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapour deposition, and field-effect transistors have been demonstrated with room-temperature mobilities as high as 10 000 cm 2 V −1 s −1 . But graphene is a gapless semiconductor and gate control of current is challenging, off-state leakage currents are high, and current does not readily saturate with drain voltage. However, various ways to overcome, adapt to, or even embrace this property are now being considered for device applications. In this work we explore through illustrative examples the potential of and challenges to graphene use for conventional and novel device applications.},
  language = {en},
  number = {31},
  urldate = {2016-02-15},
  journal = {J. Phys. D: Appl. Phys.},
  author = {Reddy, Dharmendar and Register, Leonard F. and Carpenter, Gary D. and Banerjee, Sanjay K.},
  year = {2011},
  pages = {313001}
}
@article{ramon_cmos-compatible_2011,
  title = {{CMOS}-{Compatible} {Synthesis} of {Large}-{Area}, {High}-{Mobility} {Graphene} by {Chemical} {Vapor} {Deposition} of {Acetylene} on {Cobalt} {Thin} {Films}},
  volume = {5},
  issn = {1936-0851},
  url = {http://dx.doi.org/10.1021/nn202012m},
  doi = {10.1021/nn202012m},
  abstract = {We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C2H2) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO2/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ?1600 cm2/V s and ?1000 cm2/V s, respectively, and a low trap density of ?1.2 ? 1011 cm?2.},
  number = {9},
  urldate = {2016-02-15},
  journal = {ACS Nano},
  author = {Ramón, Michael E. and Gupta, Aparna and Corbet, Chris and Ferrer, Domingo A. and Movva, Hema C. P. and Carpenter, Gary and Colombo, Luigi and Bourianoff, George and Doczy, Mark and Akinwande, Deji and Tutuc, Emanuel and Banerjee, Sanjay K.},
  month = sep,
  year = {2011},
  pages = {7198--7204}
}
@article{liu_quantum_2011,
  title = {Quantum {Transport} {Simulation} of {Strain} and {Orientation} {Effects} in {Sub}-20 nm {Silicon}-on-{Insulator} {FinFETs}},
  volume = {58},
  issn = {0018-9383},
  doi = {10.1109/TED.2010.2084090},
  abstract = {Quantum confinement in nanoscale MOSFETs based on silicon-on-insulator FinFET architecture will affect the effectiveness of strain engineering. This is because energy valley splitting due to quantum confinement may weaken the strain effect. In this paper, we investigate this phenomenon by an in-house quantum transport simulator, Schrödinger equation Monte Carlo in three dimensions, which can provide the quantum transport simulation of nanoscale 3-D MOSFET geometries such FinFETs, as well as take various scattering processes into account. Our simulation results indicate that the strain effect is more significant for devices with a channel orientation than those with a channel orientation. In addition, we also found that the strain effect is more notable when the scattering effect is considered in the quantum transport simulation. This result indicates that the scattering of hot carriers still plays a role in the carrier transport and, thus, the drain current of the nanoscale MOSFETs.},
  number = {1},
  journal = {IEEE Transactions on Electron Devices},
  author = {Liu, Keng-Ming and Register, L.F. and Banerjee, Sanjay K.},
  month = jan,
  year = {2011},
  keywords = {Device simulation, FinFETs, Logic gates, Mathematical model, Monte Carlo, Monte Carlo methods, MOSFET, nanoscale MOSFET, orientation, orientation effects, Phonons, quantum confinement, quantum transport, quantum transport simulation, Scattering, Schrodinger equation, silicon-on-insulator, silicon-on-insulator FinFET, silicon-on-insulator (SOI), Strain, strain effect},
  pages = {4--10}
}
@article{lee_mechanism_2011,
  title = {Mechanism of {VFB}/{VTH} shift in {Dysprosium} incorporated {HfO}2 gate dielectric n-{Type} {Metal}-{Oxide}-{Semiconductor} devices},
  volume = {29},
  issn = {2166-2746, 2166-2754},
  url = {http://scitation.aip.org/content/avs/journal/jvstb/29/2/10.1116/1.3562974},
  doi = {10.1116/1.3562974},
  abstract = {The authors discuss temperature-dependent dysprosium (Dy) diffusion and the diffusion-driven Dy-silicate formation process in Dy incorporated HfO 2 . The Dy-induced dipoles are closely related to the Dy-silicate formation at the high- k / SiO 2 interfaces since the V FB shift in Dy 2 O 3 is caused by the dipole and coincides with the Dy-silicate formation. Dipole formation is a thermally activated process, and more dipoles are formed at a higher temperature with a given Dy content. The Dy-silicate related bonding structure at the interface is associated with the strength of the Dy dipole moment and becomes dominant in controlling the V FB / V TH shift during the high temperature annealing in the Dy – Hf – O / SiO 2 gate oxide system. Dy-induced dipole reduces the degradation of the electron mobility.},
  number = {2},
  urldate = {2016-02-15},
  journal = {Journal of Vacuum Science \& Technology B},
  author = {Lee, Tackhwi and Choi, Kisik and Ando, Takashi and Park, Dae-Gyu and Gribelyuk, Michael A. and Kwon, Unoh and Banerjee, Sanjay K.},
  month = mar,
  year = {2011},
  keywords = {annealing, Interface diffusion, Interface structure, Ozone, X-ray photoelectron spectroscopy},
  pages = {021209}
}
@article{lee_-state_2011,
  title = {on-{State} {Performance} {Enhancement} and {Channel}-{Direction}-{Dependent} {Performance} of a {Biaxial} {Compressive} {Strained} {Quantum}-{Well} {pMOSFET} {Along} and {Channel} {Directions}},
  volume = {58},
  issn = {0018-9383},
  doi = {10.1109/TED.2011.2105876},
  abstract = {pMOSFET performance of high Ge content ( 50\%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to 80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.},
  number = {4},
  journal = {IEEE Transactions on Electron Devices},
  author = {Lee, Se-Hoon and Nainani, A. and Oh, Jungwoo and Jeon, Kanghoon and Kirsch, P.D. and Majhi, P. and Register, L.F. and Banerjee, Sanjay K. and Jammy, R.},
  month = apr,
  year = {2011},
  keywords = {anisotropic hole band structure, anisotropic transport effects, biaxial compressive strain, channel direction-dependent performance, channel orientation, channel orientations, channel transport behavior, device processing impact, direction-dependent drive current difference, drive current enhancement, Ge-Si alloys, heterostructure channel pMOSFET, hole mobility/velocity enhancement, Logic gates, low-external source-drain series resistance, MOSFET, MOSFET circuits, on-state performance enhancement, Performance evaluation, physical channel lengths, quantum well devices, quantum-well pMOSFET, S-D dopant activation anneal process, S-D series resistance, semiconductor materials, Si0.5Ge0.5, Silicon, Silicon germanium, silicon germanium (SiGe) heterostructure channel pMOSFET, Strain, Substrates, temperature-dependent mobility},
  pages = {985--995}
}
@article{lee_impact_2011,
  title = {Impact of {Millisecond} {Flash}-{Assisted} {Rapid} {Thermal} {Annealing} on {SiGe} {Heterostructure} {Channel} {pMOSFETs} {With} a {High}-k/{Metal} {Gate}},
  volume = {58},
  issn = {0018-9383},
  doi = {10.1109/TED.2011.2159862},
  abstract = {Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high-k/metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted p+ junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high- k/metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation.},
  number = {9},
  journal = {IEEE Transactions on Electron Devices},
  author = {Lee, Se-Hoon and Majhi, P. and Ferrer, D.A. and Hung, Pui-Yee and Huang, J. and Oh, J. and Loh, Wei-Yip and Sassman, B. and Min, Byoung-Gi and Tseng, Hsing-Huang and Harris, R. and Bersuker, G. and Kirsch, P.D. and Jammy, R. and Banerjee, S.K.},
  month = sep,
  year = {2011},
  keywords = {annealing, Dopant activation, Ge-Si alloys, heterostructure channel, heterostructure channel pMOSFET, high-k-metal gate, Logic gates, millisecond Flash anneal, millisecond flash-assisted rapid thermal annealing, mobility, mobility device, MOSFET, MOSFETs, rapid thermal annealing, Resistance, RTA technique, short-channel device, SiGe, Silicon, Silicon germanium, silicon germanium (SiGe), source-drain dopant activation, Strain, Substrates},
  pages = {2917--2923}
}
@article{jo_low-frequency_2011,
  title = {Low-{Frequency} {Acoustic} {Phonon} {Temperature} {Distribution} in {Electrically} {Biased} {Graphene}},
  volume = {11},
  issn = {1530-6984},
  url = {http://dx.doi.org/10.1021/nl102858c},
  doi = {10.1021/nl102858c},
  abstract = {On the basis of scanning thermal microscopy (SThM) measurements in contact and lift modes, the low-frequency acoustic phonon temperature in electrically biased, 6.7?9.7 ?m long graphene channels is found to be in equilibrium with the anharmonic scattering temperature determined from the Raman 2D peak position. With ?100 nm scale spatial resolution, the SThM reveals the shifting of local hot spots corresponding to low-carrier concentration regions with the bias and gate voltages in these much shorter samples than those exhibiting similar behaviors in the infrared emission maps.},
  number = {1},
  urldate = {2016-02-15},
  journal = {Nano Lett.},
  author = {Jo, Insun and Hsu, I-Kai and Lee, Yong J. and Sadeghi, Mir Mohammad and Kim, Seyoung and Cronin, Stephen and Tutuc, Emanuel and Banerjee, Sanjay K. and Yao, Zhen and Shi, Li},
  month = jan,
  year = {2011},
  pages = {85--90}
}
@article{jadaun_density_2011,
  title = {Density functional theory based study of graphene and dielectric oxide interfaces},
  volume = {23},
  issn = {0953-8984},
  url = {http://stacks.iop.org/0953-8984/23/i=50/a=505503},
  doi = {10.1088/0953-8984/23/50/505503},
  abstract = {We study the effects of insulating oxides in their crystalline forms on the energy band structure of monolayer and bilayer graphene using a first principles density functional theory based electronic structure method and a local density approximation. We consider the dielectric oxides SiO 2 (α-quartz) and Al 2 O 3 (alumina or α-sapphire), each with two surface terminations. Our study suggests that atomic relaxations and resulting equilibrium separations play a critical role in perturbing the linear band structure of graphene in contrast to the less critical role played by dangling bonds that result from cleaving the crystal in a particular direction. For Si-terminated quartz a Dirac cone is retained while it is restored on adding a second graphene layer for O-terminated quartz. Alumina needs more than two graphene layers to preserve the Dirac cone. Our results are, at best, semi-quantitative for the common amorphous forms of the oxides considered.},
  language = {en},
  number = {50},
  urldate = {2016-02-15},
  journal = {J. Phys.: Condens. Matter},
  author = {Jadaun, Priyamvada and Banerjee, Sanjay K. and Register, Leonard F. and Sahu, Bhagawan},
  year = {2011},
  pages = {505503}
}
@article{ferdousi_fullerene-based_2011,
  title = {Fullerene-{Based} {Hybrid} {Devices} for {High}-{Density} {Nonvolatile} {Memory}},
  volume = {10},
  issn = {1536-125X},
  doi = {10.1109/TNANO.2010.2053215},
  abstract = {We demonstrate a CMOS-compatible, nonvolatile, hybrid-memory device using fullerenes as a floating gate. In the hybrid MOS capacitors, organic fullerene molecules were encapsulated between inorganic oxides, i.e., SiO2 as a tunnel oxide and HfO2 as a control oxide. Aluminum was e-beam deposited on the fullerenes and spontaneously oxidized to act as a nucleation layer for the HfO2 control oxide. Material characterization confirmed the presence of fullerenes and high-k dielectric in the gate stack. Electrical characterization verified the memory operation of the devices. Finally, the molecular orbital energies of the fullerene molecules in the gate stack were estimated.},
  number = {3},
  journal = {IEEE Transactions on Nanotechnology},
  author = {Ferdousi, F. and Jamil, M. and Liu, H. and Kaur, S. and Ferrer, D. and Colombo, L. and Banerjee, S.K.},
  month = may,
  year = {2011},
  keywords = {aluminium, Aluminum, Circuit stability, control oxide, electron beam deposition, Fabrication, floating gate, fullerene-based hybrid devices, fullerene devices, gate stack, hafnium compounds, Hafnium oxide, HfO2, high-density nonvolatile memory, high-k dielectric, High K dielectric materials, high-k dielectric thin films, hybrid-memory device, hybrid MOS capacitors, MOS capacitors, nonvolatile memory, nucleation, nucleation layer, orbital energies, organic fullerene molecules, organic molecule, Oxidation, Permission, random-access storage, retention, silicon compounds, SiO2, Thermal stability, tunnel oxide},
  pages = {572--575}
}
@article{chang_density_2011,
  title = {Density functional study of ternary topological insulator thin films},
  volume = {83},
  url = {http://link.aps.org/doi/10.1103/PhysRevB.83.235108},
  doi = {10.1103/PhysRevB.83.235108},
  abstract = {Using an ab initio density functional theory based electronic structure method with a semilocal density approximation, we study thin-film electronic properties of two topological insulators based on ternary compounds of Tl (thallium) and Bi (bismuth). We consider TlBiX2 (X= Se, Te) and Bi2X2Y (X,Y= Se,Te) compounds which provide better Dirac cones, compared to the model binary compounds Bi2X3(X= Se, Te). With this property in combination with a structurally perfect bulk crystal, the latter ternary compound has been found to have improved surface electronic transport in recent experiments. In this article, we discuss the nature of surface states, their locations in the Brillouin zone and their interactions within the bulk region. Our calculations suggest a critical thin film thickness to maintain the Dirac cone which is significantly smaller than that in binary Bi-based compounds. Atomic relaxations or rearrangements are found to affect the Dirac cone in some of these compounds. And with the help of layer-projected surface charge densities, we discuss the penetration depth of the surface states into the bulk region. The electronic spectrum of these ternary compounds agrees very well with the available experimental results.},
  number = {23},
  urldate = {2016-02-15},
  journal = {Phys. Rev. B},
  author = {Chang, Jiwon and Register, Leonard F. and Banerjee, Sanjay K. and Sahu, Bhagawan},
  month = jun,
  year = {2011},
  pages = {235108}
}
@article{chang_dielectric_2011,
  title = {Dielectric capping effects on binary and ternary topological insulator surface states},
  volume = {84},
  url = {http://link.aps.org/doi/10.1103/PhysRevB.84.155105},
  doi = {10.1103/PhysRevB.84.155105},
  abstract = {Using a density-functional-based electronic structure method, we study the effect of crystalline dielectrics on the metallic surface states of Bismuth- and chalcogen-based binary and ternary three-dimensional topological insulator (TI) thin films. Crystalline quartz (SiO2) and boron nitride (BN) dielectrics were considered. Crystalline approximation to the amorphous quartz allows one to study the effect of oxygen coverage or environmental effects on the surface-state degradation, which has gained attention recently in the experimental community. We considered both symmetric and asymmetric dielectric cappings to the surfaces of TI thin films. Our studies suggest that BN and quartz cappings have negligible effects on the Dirac cone surface states of both binary and ternary TIs, except in the case of an oxygen-terminated quartz surface. Dangling bond states of oxygens in oxygen-terminated quartz dominate the region close to Fermi level, thereby distorting the TI Dirac cone feature and burying the Dirac point in the quartz valence-band region. Passivating the oxygen-terminated surface with atomic hydrogen removes these dangling bond states from the Fermi-surface region, and consequently the clear Dirac cone is recovered. Our results are consistent with recent experimental studies of TI surface degradation in the presence of oxygen coverage.},
  number = {15},
  urldate = {2016-02-15},
  journal = {Phys. Rev. B},
  author = {Chang, Jiwon and Jadaun, Priyamvada and Register, Leonard F. and Banerjee, Sanjay K. and Sahu, Bhagawan},
  month = oct,
  year = {2011},
  pages = {155105}
}

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