@article{sahu_effects_2010,
title = {Effects of magnetism and electric field on the energy gap of bilayer graphene nanoflakes},
volume = {81},
url = {http://link.aps.org/doi/10.1103/PhysRevB.81.045414},
doi = {10.1103/PhysRevB.81.045414},
abstract = {We study the effect of magnetism and perpendicular external electric field strengths on the energy gap of length confined bilayer graphene nanoribbons (or nanoflakes) as a function of ribbon width and length using a first-principles density-functional electronic structure method and a semilocal exchange-correlation approximation. We assume AB (Bernal) bilayer stacking and consider both armchair and zigzag edges, and for each edge type, we consider the two edge alignments, namely, α and β edge alignment. For the armchair nanoflakes we identify three distinct classes of bilayer energy gaps, determined by the number of carbon chains in the width direction (N=3p, 3p+1 and 3p+2, p is an integer), and the gaps decrease with increasing width except for class 3p+2 armchair nanoribbons. Metallic-like behavior seen in armchair bilayer nanoribbons are found to be absent in armchair nanoflakes. Class 3p+2 armchair nanoflakes show significant length dependence. We find that the gaps decrease with the applied electric fields due to large intrinsic gap of the nanoflake. The existence of a critical gap with respect to the applied field, therefore, is not predicted by our calculations. Magnetism between the layers plays a major role in enhancing the gap values resulting from the geometrical confinement, hinting at an interplay of magnetism and geometrical confinement in finite size bilayer graphene.},
number = {4},
urldate = {2016-02-15},
journal = {Phys. Rev. B},
author = {Sahu, Bhagawan and Min, Hongki and Banerjee, Sanjay K.},
month = jan,
year = {2010},
pages = {045414}
}
@article{sahu_effects_2010-1,
title = {Effects of edge magnetism and external electric field on energy gaps in multilayer graphene nanoribbons},
volume = {82},
url = {http://link.aps.org/doi/10.1103/PhysRevB.82.115426},
doi = {10.1103/PhysRevB.82.115426},
abstract = {Using first-principles density-functional theory, we study the electronic structure of multilayer graphene nanoribbons as a function of the ribbon width and the external electric field, applied perpendicular to the ribbon layers. We consider two types of edges (armchair and zigzag), each with two edge alignments (referred to as α and β alignments). We show that, as in monolayer and bilayer armchair nanoribbons, multilayer armchair nanoribbons exhibit three classes of energy gaps which decrease with increasing width. Nonmagnetic multilayer zigzag nanoribbons have band structures that are sensitive to the edge alignments and the number of layers, indicating different magnetic properties and resulting energy gaps. We find that energy gaps can be induced in ABC-stacked ribbons with a perpendicular external electric field while in other stacking sequences, the gaps decrease or remain closed as the external electric field increases.},
number = {11},
urldate = {2016-02-15},
journal = {Phys. Rev. B},
author = {Sahu, Bhagawan and Min, Hongki and Banerjee, Sanjay K.},
month = sep,
year = {2010},
pages = {115426}
}
@article{reddy_bilayer_2010,
title = {Bilayer {Pseudospin} {Field}-{Effect} {Transistor}: {Applications} to {Boolean} {Logic}},
volume = {57},
issn = {0018-9383},
shorttitle = {Bilayer {Pseudospin} {Field}-{Effect} {Transistor}},
doi = {10.1109/TED.2010.2041280},
abstract = {We have recently proposed a new type of bilayer graphene-based transistor for ultralow-power (perhaps 1000 times less compared with CMOS) room-temperature operation, namely, the bilayer pseudospin field-effect transistor (BiSFET). BiSFET operation is based on gated exciton-condensate-enhanced tunneling. Here, we discuss implementation, operation, and predicted power consumption of BiSFET-based Boolean logic gates, including an inverter, an inverter-based nor gate, and a programmable nand/or, as well as a BiSFET-based memory element. The advantages over CMOS in terms of lower voltage and power are discussed.},
number = {4},
journal = {IEEE Transactions on Electron Devices},
author = {Reddy, D. and Register, L.F. and Tutuc, E. and Banerjee, Sanjay K.},
month = apr,
year = {2010},
keywords = {Beyond complementary metal–oxidesemiconductor (CMOS) graphene, bilayer, bilayer pseudospin field-effect transistor, BiSFET-based memory element, BiSFET operation, Boolean functions, Boolean logic gates, CMOS, CMOS logic circuits, FETs, Field effect transistors, gated exciton-condensate-enhanced tunneling, graphene, graphene-based transistor, inverter-based nor gate, Logic devices, Logic gates, MOSFETs, Nanoelectronics, Physics, programmable nand, programmable or, pseudospin, Tunneling, tunnelling, ultralow-power room-temperature operation, Voltage},
pages = {755--764}
}
@article{nah_scaling_2010,
title = {Scaling {Properties} of \#x2013; {Core} \#x2013;{Shell} {Nanowire} {Field}-{Effect} {Transistors}},
volume = {57},
issn = {0018-9383},
doi = {10.1109/TED.2009.2037406},
abstract = {We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire (NW) field-effect transistors with highly doped source (S) and drain (D) and systematically investigate their scaling properties. Highly doped S and D regions are realized by low-energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the NW resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and on/off current ratio.},
number = {2},
journal = {IEEE Transactions on Electron Devices},
author = {Nah, Junghyo and Liu, En-Shao and Varahramyan, K.M. and Shahrjerdi, D. and Banerjee, Sanjay K. and Tutuc, E.},
month = feb,
year = {2010},
keywords = {B, boron, Carbon nanotubes, carrier injection, Carrier mobility, CMOS technology, contact resistance, Core–shell, Doping, effective channel length, Fabrication, FETs, field-effect transistor (FET), Field effect transistors, Germanium, highly doped drain, highly doped source, intrinsic channel resistance, Ion implantation, low-energy boron implantation, nanowire field-effect transistors fabrication, nanowire (NW), nanowires, semiconductor device manufacture, silicon–germanium, Temperature},
pages = {491--495}
}
@inproceedings{mishr_device_2010,
title = {Device and circuit performance evaluation and improvement of {SiGe} {Tunnel} {FETs}},
doi = {10.1109/ESCINANO.2010.5701031},
abstract = {Investigation on Tunnel FETs in recent years have proved them to be better than conventional MOSFETs lower subthreshold swing, lower power consumption and their scaling is not limited by quantum mechanical effects. Improvement in the on-current of TFETs has been proposed by the use of SiGe layer on the source side. This paper investigates the effect of different Ge mole fractions on the performance of various benchmark circuits (inverter, inverter with constant load, 8 bit ripple carry adder (RCA), 5 stage ring oscillator, 10 stage NAND and NOR chain). A method of the Ion/Ioff ratio of TFETs with high Ge composition, by grading the Ge composition has also been suggested.},
booktitle = {2010 {International} {Conference} on {Enabling} {Science} and {Nanotechnology} ({ESciNano})},
author = {Mishr, R. and Ghosh, Bahniman and Banerjee, Sanjay K.},
month = dec,
year = {2010},
keywords = {benchmark circuits, circuit performance evaluation, conventional MOSFET, device performance evaluation, electric current, Ge composition, Ge mole fraction effect, Ge-Si alloys, Ion/Ioff ratio, MOSFET, multilayers, power consumption, quantum mechanical effects, SiGe, SiGe layer, SiGe tunnel FET improvement, source side, subthreshold swing, TFET on-current},
pages = {1--2}
}
@article{liu_role_2010,
title = {Role of {Metal} \#x2013;{Semiconductor} {Contact} in {Nanowire} {Field}-{Effect} {Transistors}},
volume = {9},
issn = {1536-125X},
doi = {10.1109/TNANO.2009.2027119},
abstract = {In this paper, we present a systematic study of the role of metal/semiconductor nanowire (NW) contact in back-gated Ge and Si NW Schottky-barrier (SB) FETs. Our results show that the performance of such devices is largely dominated by the carrier injection efficiency at the source contact, which, in turn, is controlled by metal contact depth and gate bias. Using low-temperature annealing of back-gated Ge and Si NW SB FETs with nickel (Ni) contacts as source and drain, we monitor the evolution of the device current as the contact metal progressively diffuses into the NWs. The drain current, which is measured at a given gate and drain bias, first increases as the contact metal diffuses into the NW, reaches a maximum, and subsequently decreases. These results can be explained by the interplay between carrier injection efficiency through the metal/NW SB, which increases with the metal contact depth, and the number of available states in the NW between contact and the bottom oxide, which decreases with the metal contact depth.},
number = {2},
journal = {IEEE Transactions on Nanotechnology},
author = {Liu, En-Shao and Jain, N. and Varahramyan, K.M. and Nah, Junghyo and Banerjee, Sanjay K. and Tutuc, E.},
month = mar,
year = {2010},
keywords = {annealing, Back-gate, carrier injection efficiency, contact resistance, diffusion, FETs, Field effect transistors, gate bias, Ge, Ge-Ni, Germanium, metal contact depth, metal-semiconductor nanowire contact, Nanoelectronics, nanowire field effect transistors, nanowires, nanowires (NWs), Nickel, NW Schottky barrier FET, Schottky barriers, Schottky barriers (SBs), semiconductor-metal boundaries, semiconductor quantum wires, Si, Silicon, Si-Ni},
pages = {237--242}
}
@article{li_flicker-noise_2010,
title = {Flicker-{Noise} {Improvement} in 100-nm {Strained} {Quantum}-{Well} {Transistors} {Using} {Ultrathin} {Si} {Cap} {Layer}},
volume = {31},
issn = {0741-3106},
doi = {10.1109/LED.2009.2035140},
abstract = {This letter presents a record low flicker-noise spectral density in biaxial compressively strained p-channel 100-nm LgSi0.50Ge0.50 quantum-well FETs (QWFETs) with ultrathin Si ( 2 nm) barrier layer and 1-nm EOT hafnium silicate gate dielectric. The normalized power spectral density of Id fluctuations (SId/Id 2) in Si0.50Ge0.50 QWFETs exhibits significant improvement by ten times over surface channel unstrained Si pMOSFETs at high Vg due to strong confinement of holes within the high-mobility QW and strong quantization in the ultrathin Si barrier layer enabled by low-thermal-budget device processing. The noise behavior in strained QW devices is found to evolve from being correlated mobility fluctuation dominated across most of Vg range to being Hooge mobility fluctuation dominated at very high Vg.},
number = {1},
journal = {IEEE Electron Device Letters},
author = {Li, Feng and Lee, Se-Hoon and Fang, Zhao and Majhi, P. and Zhang, Qiming and Banerjee, Sanjay K. and Datta, S.},
month = jan,
year = {2010},
keywords = {biaxial compressively strained p-channel 100-nm quantum-well FET, EOT hafnium silicate gate dielectric, Field effect transistors, flicker noise, flicker-noise improvement, hole confinement, Hooge mobility fluctuation, low flicker-noise spectral density, low-thermal-budget device processing, MOSFET, normalized power spectral density, quantum well devices, quantum-well transistors, SiGe, SiGe quantum-well FETs (QWFET), silicon compounds, size 100 nm, surface channel MOSFETs, ultrathin Si barrier layer, ultrathin Si cap layer},
pages = {47--49}
}
@article{lee_device_2010,
title = {Device characteristics of {HfON} charge-trap layer nonvolatile memory},
volume = {28},
issn = {2166-2746, 2166-2754},
url = {http://scitation.aip.org/content/avs/journal/jvstb/28/5/10.1116/1.3481140},
doi = {10.1116/1.3481140},
abstract = {The authors studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN / Al 2 O 3 / HfON / SiO 2 / p-Si structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH 3 nitridation technique to incorporate nitrogen into the thin HfO 2 layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler–Nordheim tunnelingcurrent to increase the erase and programming speed. The trap level energy in the HfON layer was calculated by using an amphoteric model.},
number = {5},
urldate = {2016-02-15},
journal = {Journal of Vacuum Science \& Technology B},
author = {Lee, Tackhwi and Banerjee, Sanjay K.},
month = sep,
year = {2010},
keywords = {dielectric constant, Electric fields, Ozone, Photonic bandgap materials, Tunneling},
pages = {1005--1010}
}
@inproceedings{lee_hole_2010,
title = {Hole band anisotropy effect on {ON}-state performance of biaxial compressive strained {SiGe}-based short channel {QW} {pMOSFETs}: {Experimental} observations},
shorttitle = {Hole band anisotropy effect on {ON}-state performance of biaxial compressive strained {SiGe}-based short channel {QW} {pMOSFETs}},
doi = {10.1109/VTSA.2010.5488920},
abstract = {Quantum well (QW) FETs with compressively-strained SiGe channel are promising candidates for pMOSFET for future logic technology with scaled operating voltage. High hole mobility observed in strained SiGe channel layer, as compared to Si, is expected to result in enhanced performance of these devices for deep submicron channel lengths. However, most of experimental results in literature so far, focusing on [011] channel direction on relaxed (100) Si bulk substrate have shown mobility degradation (hence drive current degradation) or marginal drive current enhancement at short channel regime in pseudomorphic SiGe based channels over Si control. This has been attributed to effects of additional Coulomb scattering (from Nit and halo) and from neutral defects, as shown in Fig. 1. While these are indeed additional source of defects over Si counterpart inhibiting performance enhancement, highly anisotropic hole band structure with biaxial compressive strained SiGe channel could also play an important role on the ON-state performance degradation especially in deep submicron regime. In this paper we investigate the channel orientation dependence on the performance in an optimized Si0.5Ge0.5 QW channel. Strong drive current (mobility) enhancement is observed in [010] versus [011]. This directional dependence is further amplified at shorter channel lengths and lower temperature, and is explained on the basis of anisotropy in band structure.},
booktitle = {2010 {International} {Symposium} on {VLSI} {Technology} {Systems} and {Applications} ({VLSI}-{TSA})},
author = {Lee, Se-Hoon and Nainani, A. and Oh, Jungwoo and Kirsch, P. and Banerjee, Sanjay K. and Jammy, R.},
month = apr,
year = {2010},
keywords = {anisotropic hole band structure, Anisotropic magnetoresistance, biaxial compressive strained channel, channel orientation dependence, Coulomb scattering, deep submicron channel lengths, Degradation, FETs, Germanium silicon alloys, Ge-Si alloys, hole band anisotropy effect, Logic devices, logic technology, marginal drive current enhancement, mobility degradation, MOSFET, MOSFETs, ON-state performance, Particle scattering, quantum well devices, scaled operating voltage, short channel quantum well pMOSFET, Si0.5Ge0.5, Silicon germanium, Temperature dependence, Voltage},
pages = {126--127}
}
@article{jamil_effects_2010,
title = {Effects of {Si}-cap thickness and temperature on device performance of {Si}/{Ge} 1− x {C} x /{Si} p-{MOSFETs}},
volume = {25},
issn = {0268-1242},
url = {http://stacks.iop.org/0268-1242/25/i=4/a=045005},
doi = {10.1088/0268-1242/25/4/045005},
abstract = {This work presents the effects of Si-cap thickness and temperature on device performance of buried channel Si/Ge 1− x C x /Si p-MOSFETs. The silicon-cap thickness (3–9 nm), as well as the operating temperature (300 K down to 77 K), plays a significant role on device performance in terms of drive current, sub-threshold slope, effective hole mobility and I on – I off ratio. The 7 nm Si-capped device demonstrates highest mobility enhancement because of reduced remote Coulomb scattering. In addition, the valence band offset between the Si-cap/Ge 1− x C x interface was quantitatively extracted by fitting the stair-case behavior of split C – V characteristics with self-consistent simulations of one-dimensional Poisson and Schrodinger equations.},
language = {en},
number = {4},
urldate = {2016-02-15},
journal = {Semicond. Sci. Technol.},
author = {Jamil, Mustafa and Liu, En-Shao and Ferdousi, Fahmida and Donnelly, Joseph P. and Tutuc, Emanuel and Banerjee, Sanjay K.},
year = {2010},
pages = {045005}
}
@article{chang_analytical_2010,
title = {Analytical {Model} of {Short}-{Channel} {Double}-{Gate} {JFETs}},
volume = {57},
issn = {0018-9383},
doi = {10.1109/TED.2010.2051193},
abstract = {In this paper, we propose a compact model of the short-channel double-gate (DG) JFETs, which are devices intended for low-power logic applications. In order to make the current equation continuous through all operating conditions from the subthreshold to well above the threshold without nonphysical fitting parameters, mobile carriers in depletion regions are considered. For describing the short-channel behavior, relevant parameters extracted from the 2-D analytical solution of Poisson's equation are used to modify long-channel equations. The field-dependent mobility, velocity saturation, channel-length modulation, and drain-induced barrier lowering are considered in the short-channel analysis. Models for the DG JFET are verified through numerically simulated current-voltage characteristics. Based on the model of the DG JFETs, the advantages of the DG JFETs over single-gate MOSFETs-which may have similar fabrication requirements-with the subthreshold regime are addressed.},
number = {8},
journal = {IEEE Transactions on Electron Devices},
author = {Chang, Jiwon and Kapoor, A.K. and Register, L.F. and Banerjee, Sanjay K.},
month = aug,
year = {2010},
keywords = {analytical model, Analytical models, channel-length modulation, Doping profiles, drain-induced barrier, Fabrication, FETs, field-dependent mobility, Fitting, JFETs, Junction field-effect transistor (JFET), junction gate field effect transistors, Logic devices, low power, low-power electronics, low-power logic applications, mobile carriers, modeling, modulation, MOSFET, MOSFETs, nonphysical fitting parameters, Numerical simulation, Poisson equations, short-channel double-gate JFET, single-gate MOSFET, subthreshold swing, velocity saturation},
pages = {1846--1855}
}
@article{chang_intrinsic_2010,
title = {Intrinsic and extrinsic perturbations on the topological insulator {Bi}2Se3 surface states},
url = {http://arxiv.org/abs/1012.2927},
abstract = {Using a density functional based electronic structure method, we study the effect of perturbations on the surface state Dirac cone of a strong topological insulator Bi\$\_2\$Se\$\_3\$ from both the intrinsic and extrinsic sources. We consider atomic relaxations, and film thickness as intrinsic and interfacial thin dielectric films as an extrinsic source of perturbation to the surface states. We find that atomic relaxations has no effect on the degeneracy of the Dirac cone whereas film thickness has considerable effect on the surface states inducing a gap which increases monotonically with decrease in film thickness. We consider two insulating substrates BN and quartz as dielectric films and show that surface terminations of quartz with or without passivation plays critical role in preserving Dirac cone degeneracy whereas BN is more inert to the TI surface states. The relative orbital contribution with respect to bulk is mapped out using a simple algorithm, and with the help of it we demonstrate the bulk band inversion when spin-orbit coupling is switched on. The layer projected charge density distributions of the surface states shows that these states are not strictly confined to the surface. The spatial confinement of these states extends up to two to three quintuple layers, a quintuple layer consists of five atomic layers of Bi and Se},
urldate = {2016-02-15},
journal = {arXiv:1012.2927 [cond-mat]},
author = {Chang, Jiwon and Jadaun, Priyamvada and Register, Leonard F. and Banerjee, Sanjay K. and Sahu, Bhagawan},
month = dec,
year = {2010},
note = {arXiv: 1012.2927},
keywords = {Condensed Matter - Materials Science}
}
@article{banerjee_graphene_2010,
title = {Graphene for {CMOS} and {Beyond} {CMOS} {Applications}},
volume = {98},
issn = {0018-9219},
doi = {10.1109/JPROC.2010.2064151},
abstract = {Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated with room temperature field-effect mobilities close to 10 000 cm2/Vs. But since graphene is a gapless semiconductor, these transistors have high off-state leakage and nonsaturating drive currents. This is problematic for digital logic, but is acceptable for analog device applications such as low-noise amplifiers and radio-frequency (RF)/millimeter-wave field-effect transistors (FETs). The remarkable transport physics of graphene due to its linear bandstructure have led to novel beyond CMOS logic devices as well, such as “pseudospin” devices.},
number = {12},
journal = {Proceedings of the IEEE},
author = {Banerjee, Sanjay K. and Register, L.F. and Tutuc, E. and Basu, D. and Kim, Seyoung and Reddy, D. and MacDonald, A.H.},
month = dec,
year = {2010},
keywords = {beyond CMOS, Beyond complementary metal–oxide–semiconductor (CMOS) logic, C, Chemical vapor deposition, chemical vapour deposition, CMOS integrated circuits, CMOS logic circuits, CMOS logic devices, complementary metal-oxide-semiconductor, Dielectrics, digital logic, FETs, field-effect devices, Field effect transistors, gapless semiconductor, graphene, graphene field-effect transistors (FETs), Logic gates, mechanical exfoliation, Nanoelectronics, Physics, semiconductor industry, size 22 nm, temperature 293 K to 298 K, Transistors},
pages = {2032--2046}
}
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